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# Digital Logic Circuits (DLC) Important Questions 2012

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 Post: #1 Digital Logic Circuits (DLC) Important Questions 2012 Anna University Digital Logic Circuits (DLC) Important Questions Common To EE46:Digital Logic Circuits EC1261A Digital Logic Circuits 080280029:Digital Logic Circuits 131405:Digital Logic Circuits 10133EE406A:Digital Logic Circuits Unit I 1. Obtain the minimum SOP using Quine McCluskey’s method and verify using K – Map. F = m0 + m2 + m4 + m8 + m9 + m10 + m11+ m12 + m13 2. Determine the prime implicants of the following function using tabulation method and verify using K –Map. F = (A,B,C,D) = ∑ (3,4,5,7,9,13,14,15) 3. Design a Binary to BCD code converter and BCD to Excess -3 code converter. 4. Reduce the given expressions using Boolean algebra: (1) x’y’z’ + x’y’z + x’yz + xy’z + xyz (2) p’q’r + p’qr’ + p’qr + pqr’ + pq’r’ 5. Design a decimal adder to add two decimal digits. Unit II 1. Design a asynchronous decade counter using JK flipflop. 2. Design a 8 X1 Mux using 2 X1 multiplexers. 3. Design a synchronous counter using JK flipflop in the sequence 7,4,3,1,5,0,7…. 4. Draw and explain the block diagram of Mealy circuit 5. Design a MOD -5 synchronous counter using JK flip-flops .Draw a timing diagram. 6. Design a 2 bit Magnitude Comparator. Unit III 1. Describe the steps involved in design of asynchronous sequential circuit in detail with an example. 2. Explain the working of a 3 – input TTL totem-pole NAND gate. 3. Explain the concept and implementation of ECL logic family. 4. Explain In detail about FPGA. 5. A combinational circuit is defined by the functions . F1 (A,B,C ) =∑ (3,5,6,7) F2 (A,B,C ) =∑ (0,2,4,7).Implement the circuit with PLA Unit IV 1. Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output Z. When X1 = 0, that output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. 2. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are Y1 = x1x2 + x1 y’2 + x’2y1 Y2 = x2 + x1 y’1y2 + x’1y1 Z = x2 + y1 a) Draw the logic diagram of the circuit. b) Derive the transition table and output map. c) Obtain a flow table for the circuit. 3. The Circuit has two inputs T (toggle) and C (clock) and one output Q. The output state is complemented if T=1 and clock C changes from 1 to 0 otherwise, under any other input condition, the output Q remains unchanged. Derive the primitive flow table and implication table and the logic diagram. 4. Draw the State diagram and obtain the primitive flow table for a circuit with two inputs X1 and X2 and two outputs Z1 and Z2 that satisfies the following conditions. 1) When X1 X2 =00, output Z1 Z2 =00. 2) When X1 = 1 and X2 change from 0 to 1, the output Z1 Z2 =01. 3) When X2 = 1 and X1 change from 0 to 1, output Z1 Z2 =10. 4) Otherwise output does not change. 5. Implement the following Boolean functions with a PLA. F1 (A, B, C) = ∑ (0, 1, 2, 4) F2 (A, B, C) = ∑ (0, 5, 6, 7) F3 (A, B, C) = ∑ (0, 3, 5, 7) Unit V 1. Write VHDL program for 4x1 multiplexer. 2. Explain in detail the design procedure for register transfer language. 3. Write an HDL behavioral description of JK flip-flop using if-else statement based on the value of present state. 4. Write VHDL program for 4-bit ripple counter. 5. Explain the design procedure of RTL using VHDL For the student , by the student , to the student !! (This post was last modified: 12-05-2012 08:38 AM by Srini.)
09-05-2012 07:48 AM
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