Options
Digital Logic Circuit - Question Bank (2010)
- Digital Logic Circuit - Question Bank (2010)
-
Digital Logic Circuit - Question Bank (2010)
Srini > 10-02-2012, 09:29 PM
UNIT –I
PART – A
1. State two absorption properties of Boolean algebra.
2. State De-Morgan’s laws.
3. Show how bubbled AND gate works as NOR gate.
4. Why NAND and NOR gates are called as universal gates?
5. Why digital circuits are more frequently constructed with NAND and NOR gates than with AND and OR gates?
6. Distinguish between completely specified function and incompletely specified function.
7. Simplify the Boolean function F = (A + (BC)’)’
8. Minimize the expression using Boolean theorems F= x’y’ + x’yz + xz + xyz’. Draw the logic diagram for the minimized function.
9. If A and B are Boolean variables and if A= 1 and (A+B)’ = 0, find B.
10. Realize the function F (A, B) = A’B + AB’ using NAND gates only.
11. How many inputs and gates are required for the expression W = AB’D + ACD’ + EF
12. Name two canonical forms of Boolean algebra.
13. What is a prime implicant?
14. Express the function f(x,y,z) = x + yz as a sum of minterms.
15. For the given function write the Boolean expression in product of maxterms form
f( a,b,c) = Σm (2,3,5,6,7).
16. Plot the expression in K-map F (w, x, y) = Σ (0, 1, 3, 5, 6) + d (2, 4)
17. Show the Karnaugh map with the encircled groups for the Boolean function,
F = C’+ A’D’ + AB’D’.
18. Simplify: x + x’y
19. Express the function f(B,A) = A in terms of minterms.
20. Minimize the expression XY + X’YZ’ + YZ using Boolean theorem.
21. Find the decimal equivalent of (123)9.
22. Show that the NOR connective is not associative.
23. What happens when all the gates in a two level AND – OR gate network are replaced by NOR gates?
24.State two significant features of tabular method of minimization of Boolean functions.
25.What is two state operation?
26.What is the value of b if √ 41b = 5?
27. List out the differences between half adder and full adder.
28.Write down the truth table of a full adder.
29. Implement half adder circuit using logic gates.
30. Implement half subtractor circuit using logic gates.
31. What will be the maximum number of outputs for a decoder with a 6 bit data word?
32. List out the differences between decoder and encoder.
33. What is a multiplexer? Give its applications.
34. What is a demultiplexer? Give its applications.
35. Mention the differences between DMUX and MUX.
36. Implement the function f = Σm (0, 1, 4, 5, 7) using 8 to 1 multiplexer.
37. Design a half subtractor using 2 to 4 decoder.
38. Draw a 1 to 2 demultiplexer and 2 to1 multiplexer.
39. Implement a NAND gate using 4:1 Multiplexer.
40. Give the circuit of a half adder – subtractor.
41. What is data selector?
42. Mention the use of decoders.
UNIT –II
PART – A
1. Write the excitation tables of JK and D flip-flops.
2. Draw the logic diagram of three – bit ring counter.
3. Write the characteristic equation of JK and D flip-flop.
4. Convert an SR flip-flop to D flip-flop.
5. Define glitch.
6. Draw the block diagram of SR Flip flop and give its truth table.
7. List out the limitations of SR flip-flop.
8. Convert a D flip – flop into a T flip – flop.
9. If a serial in serial out shift register has N stages and if the clock frequency is f, what will be the time delay between input and output?
10. Distinguish between combinational and sequential circuits.
11. Describe the behaviour of SR flip-flop by means of a table.
12. How many flip-flops are required to build a counter of modulus 14 and modulus 8?
13. What is a race condition?
14. How can the race conditions be avoided in flip-flops?
15. What is a Mealy machine? Give an example.
16. Differentiate between Moore and Mealey type sequential circuits.
17. What is a state?
18. What are state diagrams and state table?
19. What are shift register counters? List two widely used shift register counters.
20. Why is state reduction necessary?
21. Derive the characteristic equation of T flip-flop.
22. What is edge triggering?
23. What is the difference between serial and parallel transfer. What type of register is used in each case?
24. When a sequential machine is said to be trivial?
25. If the input frequency of a T flip – flop is 1600 KHz, what will be the output frequency? Give reason for your answer.
UNIT –III
PART – A
1. When a sequential machine is said to be trivial?
2. List out the differences between a flip-flop and a latch.
3. Why a serial counter is referred to as asynchronous.
4. Why parallel counter is faster than ripple counter?
5. Define fundamental-mode operation.
6. Define Hazard.
7. Why critical race is said to be harmful and how it is avoided in asynchronous sequential Circuits?
8. What are cycles in asynchronous sequential circuits?
9. What are races?
10. Define static Hazard.
11. What is dynamic hazard?
12. What is critical race?
UNIT –IV
PART – A
1. What is FPGA?
2. Define Noise margin.
3. Define Fan-in and Fan out?
4. Why CMOS is preferred to TTL?
5. Compare PLA and PAL
6. What are the basic parameters to be noted before selecting an IC?
7. How does the architecture of PLA different from PROM?
8. What is the effect of increasing supply voltage on the propagation delay of the CMOS gates?
9.What is volatile memory? Give example.
10. Which is faster TTL or ECL? Which requires more power to operate?
11. Determine the Fan-out given IIH (max) = 40 μA and IOH (max) = 400 μA.
12. What is the advantage of Schottky TTL family?
13. What is an EPROM?
14. State two advantage of CMOS logic.
15. Differentiate EPROM and EEPROM.
16. Differentiate PLA, ROM and PAL.
17. Why do CMOS gates require very little power when they are not changing states?
18. Classify the basic families that belong to the bipolar families and to the MOS families.
19. What is the major difference between TTL and ECL?
20. Why does the propagation delay occur in logic circuits?
21. Draw NAND and NOR gates in CMOS logic.
UNIT V
1.Give the different operators used in VHDL.
2. What are the different types of operators?
3. What is an RTL level notation?
4. What is an ASM?
5. What is a test bench?
6. What are packages and libraries?
Attachment :
DLC-2010.pdf (Size: 163.8 KB / Downloads: 2,975)