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EE2255 Digital Logic Circuits May June 2014 Question Paper


Anna University


(Regulation 2008)

Subject Code : EE2255
Subject Name :  Digital Logic Circuits 
Type : Question Paper
Department :EEE
Semester :04

Syllabus Regulation : 2008
Attachment Type : pdf
Details : EE2255 Digital Logic Circuits   Question Paper

Sent by :Arumugam.P

Question Paper Code : 51439 
Fourth Semester 
Electrical and Electronics Engineering 
EE 2255/EE 46/EC 1261 A/080280029/10133 EE 406 A - DIGITAL LOGIC 
(Regulation 2008/2010) 
(Common to PTEE 2255 -- Digital Logic Circuits for B.E (Part-Time) Third Semester 
Electrical and Electronics Engineering — Regulation 2009) 
Time : Three hours 
Maximum : 100 marks 

Answer ALL questions. 
PART A — (10 x 2 20 marks) 
1.State De Morgan's theorem. 
2.Give examples for weighted codes. 
3.What is the drawback of SR flipflop? 
4.What is a synchronous sequential circuit? 
5.What is FPGA? 
6.List the factors used for measuring the performance of digital logic families. 
7.What is a turing machine? 
8.What are the drawbacks in designing asynchronous sequential machines? 
9.What are the advantages of hardware languages? 
10.Write VHDL code for half adder in data flow model. 

Attachment :

.pdf   EE2255 DLC June 2014.pdf (Size: 735.72 KB / Downloads: 5,596)

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