24-02-2015, 01:35 PM
VLSI Lab Manual
Jayaprakash JP Edition
Content :
1.a) STUDY OF SIMULATION OF ALL LOGIC GATES
1.b)STUDY OF SIMULATION OF A LOGIC CIRCUIT
2.a)TO DESIGN A 8 BIT RIPPLE ADDER USING THE METHOD OF INSTANTIATION
2.b)TO DESIGN AN 8 BIT RIPPLE ADDER USING CONCATENATION OPERATOR
2.c)TO DESIGN A 4 BIT MULTIPLIER
2.d)TO DESIGN A 4 to 1 MULTIPLEXER
2.e)TO DESIGN AN ADDRESS DECODER
3.a)DESIGN OF COUNTERS
3.b)DESIGN OF ACCUMULATOR
4.IMPLEMENTATION OF COMBINATIONAL AND SEQUENTIAL CIRCUITS IN FPGA
5.Layout of a simple CMOS inverter, parasitic extraction and simulation
6.TO MODEL A TWO STAGE OP-AMP
7.10 BIT NUMBER CONTROLLED OSCILLATOR USING STANDARD CELL APPROACH
Attachment : [attachment=24882]
