03-07-2018, 01:32 PM
[attachment=48712]
College Name :Varuvan Vadivelan Institute of Technology
Department :B.E. – ECE
Semester : III Year / VI Semester
Subject Code :EC6612
Subject Name :VLSI DESIGN LABORATORY
Study Material Description :
LIST OF EXPERIMENT
1 Simulation of Basic Logic Gates
2 Simulation of Half adder and Full adder
3 Simulation of Adder
4 Simulation of multiplier
5 Simulation of Binary to Gray code counter
6 Simulation of Flip Flops
7 Simulation of Pseudo Random Binary Sequence
8 Simulation of up-down counter
9 Simulation of Counter
10 Design of Sequence Detector
11 Differential Amplifier
12 CMOS Invertor
13 Layout CMOS invertor
14 Automatic layout generation
[attachment=48711]
College Name :Varuvan Vadivelan Institute of Technology
Department :B.E. – ECE
Semester : III Year / VI Semester
Subject Code :EC6612
Subject Name :VLSI DESIGN LABORATORY
Study Material Description :
LIST OF EXPERIMENT
1 Simulation of Basic Logic Gates
2 Simulation of Half adder and Full adder
3 Simulation of Adder
4 Simulation of multiplier
5 Simulation of Binary to Gray code counter
6 Simulation of Flip Flops
7 Simulation of Pseudo Random Binary Sequence
8 Simulation of up-down counter
9 Simulation of Counter
10 Design of Sequence Detector
11 Differential Amplifier
12 CMOS Invertor
13 Layout CMOS invertor
14 Automatic layout generation
[attachment=48711]