Design of Opto-Electronic Integrated Circuit and Parallel Processor in FPGA- Workshop

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Kings College of Engineering

Department of Electronics and Communication Engineering

Proudly Presents

Design of Opto-Electronic Integrated Circuit and Parallel Processor in FPGA

Workshop

on : 23rd - 25th 2013

College             : Kings College of Engineering
Event Name      : Design of Opto-Electronic Integrated Circuit and Parallel Processor in FPGA
Department       : R & D - ECE
Event Type       : Workshop
Email id             : randdece@gmail.com
Event Website    : www.kingsindia.net

Event Description  : Increase in the computation performance to a higher level by increasing speed and bandwidth with lower power consumption becomes inevitable. Opto Electronic Integrated Circuits (OEICs), circuits that monolithically integrate optical and electrical components on a single semiconductor chip, represent a device technology with potential to meet a broad range of future telecommunication and computing systems needs. The task of inserting todays OEICs into real systems and research aimed at improving and extending OEIC capabilities are progressing in parallel.  FPGAs offer tremendous performance potential and can handle number of different parallel computation applications, implemented in single clock execution time. However, much work remains to be done for achieving high-performance parallel computing by using FPGAs. This workshop intends to provide a platform whereby the participants can enhance their research capabilities and can fine-tune their skills.

Event Address      :
Kings College of Engineering
Punalkulam - 613 303

City   : Near Thanjavur, Tamil Nadu

Important Dates    :
Last date for Registration : 19.09.2013

Event Date : 23 - 25 September 2013

Contact Information:
Mr.J Niranjan Samuel - 99947 18168,
Mr.T. Pasupathi - 98941 04645,
Mr. A. Bazil 94436 77839

For More Info :

.pdf   Workshop on Kings.pdf (Size: 135.81 KB / Downloads: 232)
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    Design of Opto-Electronic Integrated Circuit and Parallel Processor in FPGA- Workshop