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CS2253 Computer Organization and Architecture - Nov / Dec 2013 Important Questions

Anna University

Department of Computer Science Engineering

Fourth Semester

(Common to Information Technology)

CS2253 Computer Organization and Architecture

Nov / Dec 2013 Important Questions 

(Regulation 2008) 

Unit I

1. Describe the role of system software to improve the performance of a computer.
2. Design a 4-bit adder/subtracted circuit using full adders and explain its function. 
3. What are the special registers in a typical computer? Explain their purposes in detail. 
4. Design a 4-bit fast adder and explain its function in detail.

Unit II

1. Draw and explain the block diagram of a complete processor. 
2. Briefly describe the design of a hardwired control unit. 
3. Explain the basic organization of a micro programmed control unit and the generation of control signals using micro program.
4. Draw the single bus and three bus organization of the data path inside a processor.

Unit III

1. Describe the role of cache memory in pipelined system. 
2. Discuss the influence of pipelining on instruction set design. 
3. What is instruction hazard? Explain the methods for dealing with the instruction hazards.
4. Design a 4-stage instruction pipeline and show how its performance is improved over sequential execution. 

Unit IV

1. What are the different secondary storage devices? Elaborate on any one of the devices. 
2. Explain how the virtual address is converted into real address in a paged virtual memory system. Explain the use of TLB
3. Explain approaches for addressing multiple-module memory systems with suitable diagrams.
4. Briefly describe magnetic disk principles and also the organization and accessing of data on a disk. 

Unit V

1. Describe the hardware mechanism for handling multiple interrupt requests.
2. What are handshaking signals? Explain the handshake control of data transfer during input and output operation.
3. What are the needs for input-output interface? Explain the functions of a typical 8-bit parallel interface in detail.
4. Design parallel priority interrupt hardware for a system with eight interrupt source.

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