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EC2354 VLSI Design Solved Question Bank - Deepak Edition

Anna University , Chennai
Department of B.E. Electronics and Communication Engineering
Sixth Semester
EC2354 VLSI Design
Solved Question Bank - Deepak Edition
(Regulation 2008)

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Content :

Typical CAD tools set
Body effect
Tristate inverter
Phases of the VLSI design flow
1. Logical verification and testing
2. Floor planning automatic place and route
3. Layout verification
4. Implementation
Transmission gate
Principle of electronic testing
Process of IC fabrication
1. Wafer processing
2. Oxidation
3. Epitaxy
4. Deposition
5. Ion implementation
6. Diffusion
Sensitivity list
Bubble pushing
Techniques of ad-HOC testing
IDDQ testing
Energy band diagram
Propogation delay
Fabrication process of the NMOS transistor
Rules for the CMOS inverters
1. Layout design rules
Active area
1. Minimum size
2. Minimum spacing
Detailed MOS gate capacitance model
CMOS process enhancement
1. Metal interconnect
2. Polysilicon interconnect
3. Local interconnect
Cut off
Chennal length modulation
1. Accumulation mode
2. Depletion mode
3. Inversion mode
Tap architecture
Instruction register
2. Sample load
3. Bypass
4. Runbist
5. Intest
Purpose of text bench
Wave form generation
1. Blocking procedural assignment
2. Non-blocking procedural assignment
Serial scan approach
Partial serial scan approach
Module instantiation
Program for half adder
Gate – level modeling
Multi output gates-gate primives
Various bidirection switches
Various region of DC transfer characteristics curve
SOI technology
Static power reduction
Dynamic power reduction
Sequencing dynamic circuits
1. Precharge mode
2. Evalution mode
Traditional mode
Silicon debug principle
Fault models
Types of failure
1. Manufacturing
2. Functional
3. Electrical
Objectives of self-test techniques
Signature analysis
Three ways of specifying delays
DC and transfer characteristics of a CMOS inverters
Divisional structure
Power dissipation
Instaneous power
Types of power dissipation
Total power
Static power dissipation
Dynamic dissipation
Inter connect scaling
Impact on design
Device model
Process variation
Problem of metastability

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